EP1SGX40GF1020C6N Altera, EP1SGX40GF1020C6N Datasheet - Page 179
EP1SGX40GF1020C6N
Manufacturer Part Number
EP1SGX40GF1020C6N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40GF1020C6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX40GF1020C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
February 2005
The bus-hold circuitry uses a resistor with a nominal resistance (R
approximately 7 kΩ to weakly pull the signal level to the last-driven state.
The chapter DC & Switching Characteristics of the Stratix GX Device
Handbook, Volume 1 gives the specific sustaining current driven through
this resistor and the overdrive current used to identify the next-driven
input level. This information is provided for each V
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Stratix GX device I/O pin provides an optional programmable pull-
up resistor during user mode. If this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the V
level of the output pin’s bank.
the weak pull-up resistor feature.
Advanced I/O Standard Support
Stratix GX device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
Note to
(1)
I/O pins
CLK[15..0]
FCLK
FPLL[7..10]CLK
Configuration pins
JTAG pins
Table 4–26. Programmable Weak Pull-Up Resistor Support
LVTTL
LVCMOS
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X 1.0
3.3-V AGP (1
TDO pins do not support programmable weak pull-up resistors.
Table
4–26:
Pin Type
×
and 2
×
)
Table 4–26
Stratix GX Device Handbook, Volume 1
Programmable Weak Pull-Up Resistor
shows which pin types support
Stratix GX Architecture
CCIO
v
v
v
(1)
voltage level.
BH
CCIO
4–113
) of
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