EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 193

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Altera Corporation
January 2006
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SU
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CO
INREG2PIPE9
INREG2PIPE18
PIPE2OUTREG2ADD
PIPE2OUTREG4ADD
PD9
PD18
PD36
CLR
CLKHL
Table 4–39. DSP Block Internal Timing Microparameter Descriptions
Symbol
Input, pipeline, and output register setup time before clock
Input, pipeline, and output register hold time after clock
Input, pipeline, and output register clock-to-output delay
Input Register to DSP Block pipeline register in 9 × 9-bit
mode
Input Register to DSP Block pipeline register in 18 × 18-bit
mode
DSP Block Pipeline Register to output register delay in Two-
Multipliers Adder mode
DSP Block Pipeline Register to output register delay in Four-
Multipliers Adder mode
Combinatorial input to output delay for 9 × 9
Combinatorial input to output delay for 18 × 18
Combinatorial input to output delay for 36 × 36
Minimum clear pulse width
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in
reported by the timing analyzer in the Quartus II software.
Stratix Device Handbook, Volume 1
Parameter
Table 4–36 on page 4–20
DC & Switching Characteristics
and as
4–23

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