EP1AGX90EF1152C6 Altera, EP1AGX90EF1152C6 Datasheet - Page 94
EP1AGX90EF1152C6
Manufacturer Part Number
EP1AGX90EF1152C6
Description
IC ARRIA GX FPGA 90K 1152FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of EP1AGX90EF1152C6
Number Of Logic Elements/cells
90220
Number Of Labs/clbs
4511
Total Ram Bits
4477824
Number Of I /o
538
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Quantity
Price
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Part Number:
EP1AGX90EF1152C6
Manufacturer:
ALTERA
Quantity:
3 000
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Part Number:
EP1AGX90EF1152C6N
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2–88
Figure 2–73. Arria GX IOE in DDR Input I/O Configuration
Notes to
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
(4) The optional PCI clamp is only available on column I/O pins.
Figure 2–74. Input Timing Diagram in DDR Mode
Arria GX Device Handbook, Volume 1
Column, Row,
Figure
Interconnect
or Local
2–73:
ioe_clk[7..0]
Input To
Logic Array
DQS Local
Bus (2)
Data at
input pin
CLK
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
B0
A0
B1
A0
B0
A1
B2
A1
B1
Input Register
Input Register
CLRN/PRN
D
ENA
CLRN/PRN
D
ENA
Input RegisterDelay
A2
(Note 1)
I
nput Pin to
B3
A2
B2
Q
Q
A3
D
ENA
CLRN/PRN
B4
A3
B3
To DQS Logic
Latch
Block (3)
Q
VCCIO
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
VCCIO
PCI Clamp (4)
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
I/O Structure
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