EPF10K130EQI240-2 Altera, EPF10K130EQI240-2 Datasheet - Page 57

• Manufacturer Part Number: EPF10K130EQI240-2
• Description: IC FLEX 10KE FPGA 130K 240-PQFP
• Manufacturer: Altera
• Series: FLEX-10KE®r

Specifications of EPF10K130EQI240-2

• Number Of Logic Elements/cells: 6656
• Number Of Labs/clbs: 832
• Total Ram Bits: 65536
• Number Of I /o: 186
• Number Of Gates: 342000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: FLEX 10KE
• Number Of Usable Gates: 130000
• Number Of Logic Blocks/elements: 6656
• # Registers: 186
• # I/os (max): 186
• Frequency (max): 333.33MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 6656
• Ram Bits: 65536
• Device System Gates: 342000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2206

Altera Corporation
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CLR
CH
CL
IOD
IOC
IOCO
IOCOMB
IOSU
IOH
IOCLR
OD1
OD2
OD3
XZ
ZX1
ZX2
ZX3
INREG
IOFD
INCOMB
Table 24. LE Timing Microparameters (Part 2 of 2)
Table 25. IOE Timing Microparameters
Symbol
Symbol
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
IOE data delay
IOE register control signal delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
IOE register hold time for data and enable signals after clock
IOE register clear time
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = on
IOE output buffer disable delay
IOE output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = on
IOE input pad and buffer to IOE register delay
IOE register feedback delay
IOE input pad and buffer to FastTrack Interconnect delay
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Note (1)
Parameter
Parameter
Note (1)
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
Condition
(2)
(3)
(4)
(2)
(3)
(4)
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