EPF10K130EQI240-2 Altera, EPF10K130EQI240-2 Datasheet - Page 46

IC FLEX 10KE FPGA 130K 240-PQFP

EPF10K130EQI240-2

Manufacturer Part Number
EPF10K130EQI240-2
Description
IC FLEX 10KE FPGA 130K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet

Specifications of EPF10K130EQI240-2

Number Of Logic Elements/cells
6656
Number Of Labs/clbs
832
Total Ram Bits
65536
Number Of I /o
186
Number Of Gates
342000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
130000
Number Of Logic Blocks/elements
6656
# Registers
186
# I/os (max)
186
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
6656
Ram Bits
65536
Device System Gates
342000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2206

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K130EQI240-2
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPF10K130EQI240-2
Manufacturer:
ALTERA
0
Part Number:
EPF10K130EQI240-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPF10K130EQI240-2N
Manufacturer:
ALTERA
0
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
46
Figure 20
Figure 20. FLEX 10KE JTAG Waveforms
Table 18
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
Captured
Table 18. FLEX 10KE JTAG Timing Parameters & Values
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
shows the timing parameters and values for FLEX 10KE devices.
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
shows the timing requirements for the JTAG signals.
t
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Parameter
t
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Altera Corporation
Min
100
50
50
20
45
20
45
t
JPXZ
Max
25
25
25
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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