EPF10K130EQI240-2 Altera, EPF10K130EQI240-2 Datasheet - Page 38
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EPF10K130EQI240-2
Manufacturer Part Number
EPF10K130EQI240-2
Description
IC FLEX 10KE FPGA 130K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K130EQI240-2
Number Of Logic Elements/cells
6656
Number Of Labs/clbs
832
Total Ram Bits
65536
Number Of I /o
186
Number Of Gates
342000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
130000
Number Of Logic Blocks/elements
6656
# Registers
186
# I/os (max)
186
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
6656
Ram Bits
65536
Device System Gates
342000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2206
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K130EQI240-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
ClockLock &
ClockBoost
Features
38
To support high-speed designs, FLEX 10KE devices offer optional
ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)
used to increase design speed and reduce resource usage. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by resource sharing within the device. The ClockBoost feature
allows the designer to distribute a low-speed clock and multiply that clock
on-device. Combined, the ClockLock and ClockBoost features provide
significant improvements in system performance and bandwidth.
All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices,
support ClockLock and ClockBoost circuitry. EPF10K50S and
EPF10K200S devices support this circuitry. Devices that support Clock-
Lock and ClockBoost circuitry are distinguished with an “X” suffix in the
ordering code; for instance, the EPF10K200SFC672-1X device supports
this circuit.
The ClockLock and ClockBoost features in FLEX 10KE devices are
enabled through the Altera software. External devices are not required to
use these features. The output of the ClockLock and ClockBoost circuits is
not available at any of the device pins.
The ClockLock and ClockBoost circuitry locks onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the
Altera software, the GCLK1 pin can feed both the ClockLock and
ClockBoost circuitry in the FLEX 10KE device. However, when both
circuits are used, the other clock pin cannot be used.
Altera Corporation