EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 61

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Figure 3–15. Mixed-Port Read-During-Write Timing Waveforms
December 2010 Altera Corporation
True Dual-Port Mode
q_a (asynch)
address
byteena
data_a
wrena
rdena
clk_a
Figure 3–15
mode with unregistered outputs.
Arria II M9K and M144K blocks support true dual-port mode. Sometimes called
bidirectional dual-port, this mode allows you to perform any combination of two-port
operations: two reads, two writes, or one read and one write at two different clock
frequencies. True dual-port memory supports input and output clock mode in
addition to the independent clock mode.
Figure 3–16
Figure 3–16. Arria II True Dual-Port Memory
The widest bit configuration of the M9K and M144K blocks in true dual-port mode
are:
■
■
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers.
M9K: 512 × 16-bit (or 512 × 18-bit with parity)
M144K: 4K × 32-bit (or 4K × 36-bit with parity)
shows timing waveforms for read and write operations in mixed-port
shows the true dual-port RAM configuration.
A123
01
A0 (old data)
B456
10
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
enable_a
rden_a
aclr_a
q_a[]
A0
D
clock_a
old
D
old
23
C789
00
Arria II Device Handbook Volume 1: Device Interfaces and Integration
B423
DDDD
A1(old data)
addressstall_b
address_b[]
byteena_b[]
enable_b
data_b[ ]
clock_b
wren_b
rden_b
A1
EEEE
11
aclr_b
q_b[]
DDDD
FFFF
EEEE
3–15