EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 529

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Table 2–10. Transmitter Phase Compensation FIFO Read Clocks for Arria II Devices
December 2010 Altera Corporation
Non-Bonded Channel Configuration
×4 Bonded Channel Configuration
×8 Bonded Channel Configuration
Configuration
1
1
1
Table 2–10
Quartus II software selects in various configurations.
To ensure that you understand the 0 PPM clock driver rule, the Quartus II software
expects the “GXB 0 PPM Core Clock Setting” user assignment whenever you use the
tx_coreclk port to drive the transmitter phase compensation FIFO write clock.
Failure to make this assignment when using the tx_coreclk port results in a
Quartus II compilation error.
GXB 0 PPM Core Clock Setting
The GXB 0 PPM core clock setting is intended for advanced users who know the
clocking configuration of the entire system and want to reduce the FPGA fabric global
and regional clock resource utilization. The GXB 0 PPM core clock setting allows the
following clock drivers to drive the tx_coreclk ports:
■
■
■
■
■
The Quartus II software does not allow gated clocks or clocks generated in the FPGA
logic to drive the tx_coreclk ports.
Because the GXB 0 PPM core clock setting allows FPGA CLK input pins and
transceiver REFCLK pins as the clock driver, the Quartus II compiler cannot determine
if there is a 0 PPM difference between the FIFO write clock and read clock for each
channel.
You must ensure that the clock driver for all connected tx_coreclk ports has a 0 PPM
difference with respect to the FIFO read clock in those channels.
tx_clkout in non-bonded channel configurations
coreclkout in bonded channel configurations
FPGA CLK input pins
Transceiver REFCLK pins
Clock output from the left-corner PLLs (PLL_1 and PLL_4)
lists the transmitter phase compensation FIFO read clocks that the
Parallel transmitter PCS clock from the
local clock divider in the associated
channel (tx_clkout)
Low-speed parallel clock from the CMU0
clock divider of the associated
transceiver block (coreclkout)
Low-speed parallel clock from the CMU0
clock divider of the master transceiver
block (coreclkout from master
transceiver block)
Without Byte Serializer
Transmitter Phase Compensation FIFO Read Clock
Arria II Device Handbook Volume 2: Transceivers
Divide-by-two version of the parallel
transmitter PCS clock from the local
clock divider in the associated channel
(tx_clkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock
divider of the associated transceiver
block (coreclkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock
divider of the master transceiver block
(coreclkout from master transceiver
block)
With Byte Serializer
2–39