EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 518

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–28
Table 2–8. Receiver Datapath Clock Frequencies in PCIe ×8 Functional Modes for Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Arria II Device Handbook Volume 2: Transceivers
Notes to
(1) 250 MHz when you enable the PCIe hard IP.
(2) Arria II GZ devices only.
PCIe ×8 (Gen 2)
Functional Mode
PCIe ×8 (Gen 1)
Table
Input Reference Clocks
2–8:
(2)
The parallel recovered clock from the receiver PMA in each channel clocks the word
aligner and write side of the rate match FIFO in that channel. The low-speed parallel
clock from the CMU0 clock divider of the master transceiver block clocks the read port
of the rate match FIFO, the 8B/10B decoder, and the write port of the byte deserializer
(if enabled) in all eight channels. The low-speed parallel clock or its divide-by-two
version (if byte-deserializer is enabled) clocks the write port of the receiver phase
compensation FIFO in all eight channels. It is also driven on the coreclkout port as
the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to latch
the receiver data and status signals in the FPGA fabric for all eight bonded channels.
Both the receiver phase compensation FIFO pointers and the control circuitry from
Channel 0 in the master transceiver block are shared by the receiver phase
compensation FIFOs across all eight channels in PCIe ×8 mode.
Table 2–8
The FPGA fabric-transceiver interface clocks consist of clock signals from the FPGA
fabric to the transceiver blocks and clock signals from the transceiver blocks to the
FPGA fabric.
The FPGA fabric-transceiver interface clocks are divided into the following three
categories:
■
■
■
The CMU PLLs and receiver CDRs in each transceiver block derive the input
reference from one of the following sources:
■
■
■
■
“Input Reference Clocks” on page 2–28
“Phase Compensation FIFO Clocks” on page 2–29
“Other Transceiver Clocks” on page 2–29
refclk0 and refclk1 pins of the same transceiver block
refclk0 and refclk1 pins of other transceiver blocks on the same side of the
device using the ITB clock network
CLK input pins on the FPGA global clock network
Clock output pins from the left PLLs in the FPGA fabric
Data Rate
(Gbps)
2.5
5
lists the receiver datapath clock frequencies in PCIe ×8 functional mode.
Recovered
Frequency
Serial
Clock
(GHz)
1.25
2.5
Transmitter PCS Clock
Parallel Recovered
clock and Parallel
Frequency (MHz)
250
500
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface
Without Byte
FPGA Fabric-Transceiver Interface Clocking
Serializer
—
—
December 2010 Altera Corporation
(1)
Clock Frequency
Serializer (MHz)
With Byte
125
250