EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 497
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
In non-bonded channel configurations, the high-speed serial clock and low-speed
parallel clock in each channel are generated independently by its local clock divider,
as shown in
skew. The transmitter phase compensation FIFO in each non-bonded channel has its
own pointers and control logic that can result in unequal latency in the transmitter
phase compensation FIFO of each channel. The higher transceiver clock skew and
unequal latency in the transmitter phase compensation FIFO in each channel can
result in higher channel-to-channel skew in non-bonded channel configurations.
In bonded channel configurations, the high-speed serial clock and low-speed parallel
clock for all bonded channels are generated by the same CMU0 clock divider block
(refer to
The transmitter phase compensation FIFO in all bonded channels share common
pointers and control logic generated in the CMU0 channel, resulting in equal latency in
the transmitter phase compensation FIFO of all bonded channels. The lower
transceiver clock skew and equal latency in the transmitter phase compensation
FIFOs in all channels provide lower channel-to-channel skew in bonded channel
configurations.
Non-Bonded Channel Configurations
The following functional modes support non-bonded transmitter channel
configuration:
■
■
■
■
■
■
■
PCIe ×1—Gen1 and Gen2 (Gen2 for Arria II GZ only)
Gigabit Ethernet (GIGE)
Serial RapidIO (SRIO)
SONET/SDH
SDI
Common Public Radio Interface (CPRI)/OBSAI
Basic (except Basic ×4 mode)
Figure 2–6 on page
Figure 2–5 on page
2–11), resulting in lower channel-to-channel clock skew.
2–8, resulting in higher channel-to-channel clock
Arria II Device Handbook Volume 2: Transceivers
2–7
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