EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 476

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–90
Figure 1–86. Datapath for the PRBS Mode
Note to
(1) Serial loopback can be dynamically enabled through the rx_seriallpbken port.
Table 1–22. Patterns in PRBS Mode for Arria II Devices (Part 1 of 2)
Arria II Device Handbook Volume 2: Transceivers
Fabric
FPGA
Patterns
PRBS 10
PRBS 23
Figure
PRBS 7
PRBS 8
1–86:
X
X
Figure 1–86
the serializer. The verifier checks the data from the word aligner.
PRBS mode has two pattern generator options, selectable in the BIST tab of the
MegaWizard Plug-In Manager when you choose PRBS as a sub protocol under Basic
functional mode.
■
■
Table 1–22
Polynomial
X
X
23
10
7
8
+ X
+ X
+ X
+ X
PRBS7, PRBS8, PRBS10, and PRBS23 generator and verifier—This is the generator
and verifier interface with the serializer and deserializer in the PMA blocks. The
advantage of using a PRBS data stream is that the randomness yields an
environment that stresses the transmission medium. In the data stream, you can
observe both random jitter and deterministic jitter using a time interval analyzer,
bit error rate tester, or oscilloscope.
High-frequency and low-frequency pattern generator—The high-frequency
patterns generate alternate ones and zeros and the low-frequency patterns
generate five ones and five zeroes in single width mode, and ten ones and ten
zeroes in double width mode. These patterns do not have a corresponding verifier.
The PRBS repeats after completing an iteration. The number of bits the PRBSx
pattern sends before repeating the pattern is (2^×-1) bits. This mode is available as
a sub protocol under Basic functional mode.
6
7
18
7
+ 1
+ 1
+ 1
+ 1
lists various PRBS patterns and corresponding word alignment patterns.
tx_clkout[0]
Compensation
wrclk
shows the datapath for the PRBS patterns. The generated pattern is sent to
Channel Width
TX Phase
of 8-Bit
FIFO
rdclk
10 bit
8 bit
8 bit
8 bit
(1)
/2
wrclk
Word Alignment
Byte Serializer
16’h3040
/2
16’hFF5A
Receiver Channel PCS
16’hFFFF
10’h3FF
Transmitter Channel PCS
Pattern
rdclk
Chapter 1: Transceiver Architecture in Arria II Devices
8B/10B Encoder
Low-Speed Parallel Clock
Frequency Pattern Generator
PRBS, High Frequency, Low
Low-Speed Parallel Clock
Parallel Recovery Clock
Maximum Data Rate
PRBS Verifier
December 2010 Altera Corporation
3.125
2.5
2.5
2.5
Serial Clock
High-Speed
Transmitter Channel
Receiver Channel
PMA
PMA
Test Modes
(1)