EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 470

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Arria II Device Handbook Volume 2: Transceivers
c
Figure 1–79
columns must be deleted.
Figure 1–79. Example of Rate Match Deletion in XAUI Mode
Figure 1–80
columns must be inserted.
Figure 1–80. Example of Rate Match Insertion in XAUI Mode
The rate match FIFO does not insert or delete code groups automatically to overcome
FIFO empty or full conditions. In this case, the rate match FIFO asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively. You must then assert
the rx_digitalreset signal to reset the receiver PCS blocks.
rx_rmfifodatadeleted
rx_rmfifodatainserted
shows an example of rate match deletion in the case where three ||R||
shows an example of rate match insertion in the case where two ||R||
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datain[2]
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datain[0]
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Chapter 1: Transceiver Architecture in Arria II Devices
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December 2010 Altera Corporation
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