EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 400

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Arria II Device Handbook Volume 2: Transceivers
f
Byte Serializer
In Arria II GX devices, you cannot enable the byte serializer in double-width mode.
However, in Arria II GZ devices, you can enable both double-width and the byte
serializer to achieve a 32- or 40-bit PCS-FPGA interface.
Figure 1–13
Figure 1–13. Byte Serializer Datapath for Arria II GX Devices
The byte serializer divides the input datapath width by two. This allows you to run
the transceiver channel at higher data rates while keeping the FPGA fabric frequency
within the maximum limit. This module is required in configurations that exceed the
FPGA fabric-to-transceiver interface clock upper frequency limit. It is optional in
configurations that do not exceed the FPGA fabric-to-transceiver interface clock
upper frequency limit.
For example, if you want to run the transceiver channel at 3.125 Gbps, without the
byte serializer, the FPGA fabric interface clock frequency must be 312.5 MHz
(3.125 Gbps/10), which violates the FPGA fabric interface frequency limit. When you
use the byte serializer, the FPGA fabric interface frequency is 156.25 MHz
(3.125 Gbps/20).
For more information about the maximum frequency limit for the FPGA
fabric-to-transceiver interface, refer to the
The byte serializer forwards the data from the TX phase compensation FIFO LSByte
first. For example, assuming a channel width of 20 bits, the byte serializer sends out
the least significant word datain[9:0] of the parallel data from the FPGA fabric,
followed by datain[19:10].
The data from the byte serializer is forwarded to the 8B/10B encoder if the module is
enabled and the input data width is 16 bits. Otherwise, the output is forwarded to the
serializer module in the transceiver PMA block.
TX Phase-Compensation
shows the byte serializer datapath for Arria II GX devices.
FIFO (16 or 20 bits)
Input Data from the
Byte Serializer
Device Datasheet for Arria II
/2
Chapter 1: Transceiver Architecture in Arria II Devices
Low-Speed Parallel Clock
Output Data to the
8B/10B Encoder (8 bits)
or Serializer (8 or 10 bits)
December 2010 Altera Corporation
Transmitter Channel Datapath
Devices.