EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 254

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–14
Figure 8–10. Data Realignment Timing
Arria II Device Handbook Volume 1: Device Interfaces and Integration
rx_channel_data_align
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes
channel-to-channel skew on the received serial data streams. If you enabled the DPA
block, the received data is captured with different clock phases on each channel and
might cause the received data to be misaligned from channel to channel. To
compensate for the channel-to-channel skew and establish the correct received word
boundary at each channel, each receiver channel has a dedicated data realignment
circuit that realigns the data by inserting bit latencies into the serial stream.
An optional signal (rx_channel_data_align) controls the bit insertion of each receiver
independently controlled from the internal logic. The data slips one bit on the rising
edge of rx_channel_data_align. The following are requirements for the
rx_channel_data_align signal:
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■
■
■
■
Figure 8–10
factor set to 4.
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The programmable bit rollover point can be from 1 to 11 bit-times,
independent of the deserialization factor. The programmable bit rollover point must
be set to equal to or greater than the deserialization factor, allowing enough depth in
the word alignment circuit to slip through a full word. You can set the value of the bit
rollover point using the ALTLVDS megafunction. An optional status signal
(rx_cda_max) is available to the FPGA fabric from each channel to indicate when the
preset rollover point is reached.
An edge-triggered signal
The minimum pulse width is one period of the parallel clock in the logic array
The minimum low time between pulses is one period of the parallel clock
Holding rx_channel_data_align does not result in extra slips
Valid data is available two parallel clock cycles after the rising edge of the
rx_channel_data_align signal
rx_outclock
rx_inclock
rx_out
rx_in
shows receiver output after one bit-slip pulse with the deserialization
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
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Differential Receiver