EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 235
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Figure 7–26. IOE Input Registers for Arria II GZ Devices
Notes to
(1) You can bypass each register block in this path.
(2) This is the 0-phase resynchronization clock.
(3) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a GCLK line.
(4) This input clock comes from the CQn logic block.
(5) This resynchronization clock comes from a PLL through the clock network (resync_ck_2× ).
(6) The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL, the I/O clock divider can also be fed by the DQS bus or CQn
(7) The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.
(8) You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data
(9) The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS, and DQSn
(10) The bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/
December 2010 Altera Corporation
DQS/CQ (3) , (9)
DQSn (9)
CQn (4)
bus.
rate register to feed dataout.
signals are automatically inverted.
synchronization register to feed dataout.
Figure
Differential
7–26:
Input
Buffer
DQ
Resynchronization Clock
(resync_clk_2×) (5)
Figure 7–26
consists of the DDR input registers, resynchronization registers, and HDR block. You
can bypass each block of the input path.
0
1
Double Data Rate Input Registers
Input Reg A
Input Reg B
D
D
DFF
DFF
Q
Q
neg_reg_out
I
I
shows the registers available in the Arria II GZ input path. The input path
Input Reg C
D
DFF
Q
I
Alignment and Synchronization Registers
datain [0]
datain [1]
<bypass_output_register> (10)
(Note 1)
(2)
D
D
DFF
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DFF
Q
Q
Divider (6)
I/O Clock
dataout
dataout
Half-Rate Resynchronization Clock (resync_clk_1×)
Half Data Rate Registers
D
D
D
D
DFF
DFF
DFF
DFF
Q
Q
Q
Q
D
D
DFF
DFF
Q
Q
dataout [0] (7)
dataout [1] (7)
To Core
To Core
7–39
directin
0
1
0
1
dataoutbypass
dataout [3] (7)
to core (7)
dataout[2] (7)
To Core
To Core
(8)
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