EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 187

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II Devices
Termination Schemes for I/O Standards
Figure 6–12. HSTL I/O Standard Termination for Arria II Devices
Note to
(1) Applicable to Arria II GZ devices only.
December 2010 Altera Corporation
External
On-Board
Termination
Termination
OCT
in Bi-
Directional
Pins (1)
OCT
Receive (1)
OCT
Transmit
Figure
6–12:
Series OCT
50
Series OCT 50
Transmitter
Transmitter
Transmitter
Transmitter
Figure 6–12
V
CCIO
100
100
HSTL Class I
50
50
50
50
shows the details of HSTL I/O termination on Arria II devices.
V REF
V REF
50
50
V REF
V TT
V TT
V
CCIO
V
100
CCIO
100
100
100
Series
OCT 50
Receiver
Receiver
Receiver
Receiver
Parallel OCT
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Series OCT
25
Series OCT 25
Transmitter
Transmitter
Transmitter
Transmitter
V
CCIO
100
100
V TT
V TT
HSTL Class II
V TT
50
50
50
50 8
V REF
50
50
V REF
50
50
50
V REF
V TT
V TT
V
CCIO
V
100
100
CCIO
100
100
Receiver
Receiver
Receiver
Receiver
Series
OCT 25
Parallel OCT
6–29