EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 168
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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6–10
I/O Structure
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Table 6–6. Pin Migration Across Densities in Arria II GZ Devices
The I/O element (IOE) in the Arria II devices contains a bidirectional I/O buffer and
I/O registers to support a completely embedded bidirectional single data rate (SDR)
or double data rate (DDR) transfer. The IOEs are located in I/O blocks around the
periphery of the Arria II device. There are up to four IOEs per row I/O block and four
IOEs per column I/O block. The row IOEs drive row, column, or direct link
interconnects. The column IOEs drive column interconnects.
The Arria II bidirectional IOE supports the following features:
■
■
■
■
■
■
■
■
■
■
■
■
1152-pin Flip Chip
FBGA
1517-pin Flip Chip
FBGA
Note to
(1) Each transceiver channel consists of two Tx pins, two Rx pins and a transceiver clock pin.
Programmable input delay
Programmable output-current strength
Programmable slew rate
Programmable bus-hold
Programmable pull-up resistor
Programmable output delay
Open-drain output
R
R
R
Dynamic OCT for Arria II GZ devices
PCI clamping diode
S
D
T
Package
OCT
OCT for Arria II GZ devices
OCT
Table
6–6:
I/O
Clock
XVCR channel
I/O
Clock
XVCR channel
Pin Type
EP2AGZ225
550
726
16
24
4
8
Chapter 6: I/O Features in Arria II Devices
EP2AGZ300
(Note 1)
Device
December 2010 Altera Corporation
550
726
16
24
4
8
(Part 2 of 2)
EP2AGZ350
550
726
I/O Structure
16
24
4
8
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