EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 50
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 50
Figure 10. Design Space Explorer Window
f
f
For more information, refer to the
Quartus II Handbook.
The Optimization Advisors provide guidance in making settings that optimize your
design. On the Tools menu, point to Advisors, and click Resource Optimization
Advisor, or Timing Optimization Advisor. Evaluate the options and choose the
settings that best suit the requirements.
For more information about the various timing optimization settings in the Quartus II
software as well as the timing optimization techniques, refer to the
Integrated Synthesis
Timing Optimization
Recommended Timing Optimization and Analysis Assignments
The assignments and settings described in this section are not turned on in the
software by default for all designs, but are important for large designs.
Turn on Optimize fast-corner timing on the Fitter Settings page in the Settings
dialog box, as in
timing requirements at the Fast Timing process corner and operating condition, as
well as at the Slow Timing corner. Therefore, turning on this option helps create a
design implementation that is more robust across process, temperature, and voltage
variations.
Figure
chapter in volume 1 of the Quartus II Handbook and the
chapter in volume 2 of the Quartus II Handbook.
11. When this option is on, the design is optimized to meet its
Design Space Explorer
chapter in volume 2 of the
© November 2008 Altera Corporation
Quartus II
Area and
Verification