EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 34
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 34
Chip-Wide Reset
Register Power-Up Level
If the purpose of turning off the clock is to stop clocking registers to prevent the
register output change, you can control the input to the register instead, as illustrated
in
keeps toggling. This ensures the register output is synchronized with other register
outputs that use the same clock. Gating the clock to the register introduces additional
delay to the clock and the register output may not be synchronized with other signals.
Figure 6. Synchronous Clock Enable
If you must implement gated clocks using logic resources, register the gating signal
that enables or disables the clock to filter out any glitches that might appear in the
gating signal. Otherwise, glitches from the gating signal can propagate to the clock
signal. Also, gating the clock signal at the source minimizes the clock delay
differences between different blocks within the design that are clocked by the same
clock signal.
A Cyclone III device supports the chip-wide reset that clears all registers in the device,
including registers of the M9K blocks. This reset overrides all other control signals of
the registers and allows you to re-initialize the device at any given time.
To enable the chip-wide reset from the Quartus II software, on the Assignments menu,
click Settings. Under Device, click Device & Pin Options. Then, on the General
window, turn on Enable device-wide reset (DEV_CLRn). Enable this feature before
compiling your design. When the chip-wide reset option is turned on, holding the
DEV_CLRn pin low resets all the registers. When this feature is turned off, the
DEV_CLRn pin functions as a normal user I/O pin.
You can select the power-up level of the registers in the Cyclone III to be either high or
low. By default, when the device powers up, all registers in the device are cleared and
the registered output signals drive low. Setting the register to power up high prevents
the activation of another device’s active-low input when the Cyclone III device is
powered up. The register power-up high feature can also be used as a system reset
signal when the Cyclone III device is powered up. If a register is set to power-up high,
the register output will remain high until the asynchronous clear signal is asserted or
a low data signal is clocked in. You can use the asynchronous preset signal to ensure
that the register output remains high after the device is powered up. Set the register in
the Quartus II design to power up high before design compilation.
In the Quartus II integrated synthesis, you can apply the Power-Up Level logic option
in the Assignment Editor, with a Tcl assignment, or create an altera_attribute
assignment in your source code.
Figure
6. The enable signal controls the input to the register, while the clock signal
Data
Enable
D
Q
© November 2008 Altera Corporation
Design and Compilation