EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 27
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Board Design Considerations
© November 2008 Altera Corporation
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Configuration Devices
The EPCS devices (EPCS4, EPCS16, EPCS64, and EPCS128) are used in the AS
configuration scheme for Cyclone III devices.
For information about the EPCS devices, refer to the
(EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Configuration Handbook.
EPCS Connection
The four-pin interface of the EPCS device consists of a serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and an active-low chip select (nCS). This
four-pin interface connects to the Cyclone III device pins, which are the DCLK,
DATA[0], DATA[1], and FLASH_nCE, respectively. The Cyclone III device’s
FLASH_nCE pin functions as the nCEO pin in AS configuration scheme, and DATA[1]
pin functions as the ASDO pin in AS configuration scheme.
When connecting a serial configuration device to the Cyclone III device in single
device AS configuration, you must connect a 25-
serial configuration device for the DATA[0]. In single device AS configuration, the
board trace length between the serial configuration device to the Cyclone III device
should not exceed 10 inches.
For more information on the connections for AS configuration scheme, refer to the
Configuring Cyclone III Devices
EPCS Support for Cyclone III Devices
In Cyclone III devices, the active master clock frequency runs at a maximum of 40
MHz, and at a typical 30 MHz. Cyclone III devices work only with EPCS devices that
support up to 40 MHz. Existing batches of EPCS4 manufactured on 0.15 µm process
geometry support AS configuration in Cyclone III devices up to 40 MHz. However,
batches of EPCS4 manufactured on 0.18 µm process geometry support only up to 20
MHz and do not support AS configuration in Cyclone III devices. The EPCS16 and
EPCS64 serial configuration devices are not affected.
For information about product traceability and transition date to differentiate
between 0.15 µm process geometry and 0.18 µm process geometry EPCS4 serial
configuration devices, refer to the PCN 0514 Manufacturing Changes on EPCS Family
process change notification on the Altera website at www.altera.com.
1
If you use the AS configuration scheme for Cyclone III devices, the V
the I/O Bank 1 must be 3.3 V. If you use the AP configuration scheme for
Cyclone III devices, the V
and must be either 1.8, 2.5, 3.0 or 3.3 V. Altera recommends not to use level
shifters between a configuration device and the Cyclone III device in any
active (AS or AP) configuration scheme.
chapter in volume 1 of the Cyclone III Device Handbook.
CCIO
of I/O Banks 1, 6, 7 and 8 must be the same
Ω
series resistor at the near end of the
Serial Configuration Devices
in volume 2 of the
CCIO
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