EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 267
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
IEEE Std. 1149.1 BST Architecture
© December 2009
CIII51014-2.2
f
1
Altera Corporation
This chapter provides guidelines on using the IEEE Std. 1149.1 boundary-scan test
(BST) circuitry in Cyclone
BST architecture tests pin connections without using physical test probes, and
captures functional data while a device is operating normally. Boundary-scan cells
(BSCs) in a device can force signals onto pins or capture data from pin or logic array
signals. Forced test data is serially shifted into the boundary-scan cells. Captured data
is serially shifted out and externally compared to expected results.
This chapter contains the following sections:
■
■
■
■
■
Cyclone III device family operating in the IEEE Std. 1149.1 BST mode use four
required pins:
■
■
■
■
The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins
have weak internal pull-up resistors. The TDO output pin and all the JTAG input pins
are powered by the 2.5-V or 3.0-V V
JTAG configuration.
For recommendations on how to connect a JTAG chain with multiple voltages across
the devices in the chain, refer to
For more information about the description and functionality of all JTAG pins,
registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)
controller, refer to
“IEEE Std. 1149.1 BST Architecture” on page 12–1
“IEEE Std. 1149.1 BST Operation Control” on page 12–2
“I/O Voltage Support in a JTAG Chain” on page 12–5
“Guidelines for IEEE Std. 1149.1 BST” on page 12–6
“Boundary-Scan Description Language Support” on page 12–7
TDI
TDO
TMS
TCK
AN39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Testing for the Cyclone III Device Family
12. IEEE 1149.1 (JTAG) Boundary-Scan
®
III device family (Cyclone III and Cyclone III LS devices).
“I/O Voltage Support in a JTAG Chain” on page
CCIO
supply. All user I/O pins are tri-stated during
Cyclone III Device Handbook, Volume 1
Devices.
12–5.