EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 68
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 68 of 350
- Download datasheet (8Mb)
5–4
Clock Control Block
Cyclone III Device Handbook, Volume 1
f
If you do not use dedicated clock pins to feed the GCLKs, you can use them as
general-purpose input pins to feed the logic array. However, when using them as
general-purpose input pins, they do not have support for an I/O register and must
use LE-based registers in place of an I/O register.
For more information about how to connect the clock and PLL pins, refer to the
Cyclone III Device Family Pin Connection Guidelines
The clock control block drives GCLKs. Clock control blocks are located on each side of
the device, close to the dedicated clock input pins. GCLKs are optimized for
minimum clock skew and delay.
Table 5–2
GCLKs.
Table 5–2. Clock Control Block Inputs
In the Cyclone III device family, dedicated clock input pins, PLL counter outputs,
dual-purpose clock I/O inputs, and internal logic can all feed the clock control block
for each GCLK. The output from the clock control block in turn feeds the
corresponding GCLK. The GCLK can drive the PLL input if the clock control block
inputs are outputs of another PLL or dedicated clock input pins. The clock control
blocks are at the device periphery; there are a maximum of 20 clock control blocks
available per Cyclone III device family.
The control block has two functions:
■
■
Dedicated clock inputs
Dual-purpose clock
(DPCLK and CDPCLK)
I/O input
PLL outputs
Internal logic
Dynamic GCLK clock source selection (not applicable for DPCLK or CDPCLK and
internal logic input)
GCLK network power down (dynamic enable and disable)
lists the sources that can feed the clock control block, which in turn feeds the
Input
Dedicated clock input pins can drive clocks or global signals, such as
synchronous and asynchronous clears, presets, or clock enables onto
given GCLKs.
DPCLK and CDPCLK I/O pins are bidirectional dual function pins that
are used for high fan-out control signals, such as protocol signals,
TRDY and IRDY signals for PCI, via the GCLK. Clock control blocks
that have inputs driven by dual-purpose clock I/O pins are not able to
drive PLL inputs.
PLL counter outputs can drive the GCLK.
You can drive the GCLK through logic array routing to enable internal
logic elements (LEs) to drive a high fan-out, low-skew signal path.
Clock control blocks that have inputs driven by internal logic are not
able to drive PLL inputs.
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
on the Altera
Description
© December 2009 Altera Corporation
®
website.
Clock Networks
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