EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 338
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 338 of 350
- Download datasheet (8Mb)
2–20
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification
Cyclone III Device Handbook, Volume 2
Output jitter
(peak to peak)
t
t
t
Notes to
(1) Applicable for true and emulated mini-LVDS with three-resistor network transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS with three-resistor
(3) t
RISE
FALL
LOCK
(3)
network transmitter is supported at the output pin of all I/O banks.
LOC K
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
2–28:
20 – 80%,
C
20 – 80%,
C
LOAD
LOAD
Table 2–29. Cyclone III LS Devices True LVDS Transmitter Timing Specifications
(Preliminary)
f
frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) True LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6).
(2) t
HSC LK
DUTY
LOCK
= 5 pF
= 5 pF
Modes
(2)
Symbol
LOC K
(input clock
—
—
Table
is the time required for the PLL to lock from the end of device configuration.
2–29:
Min
Modes
—
—
—
—
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
C7 and I7
500
500
Typ
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
Max
500
—
—
C7 and I7
1
402.5
402.5
Max
370
370
370
370
370
740
740
740
740
740
200
500
Min
55
1
—
—
—
—
(Note 1)
Chapter 2: Cyclone III LS Device Data Sheet
,
(2)
C8
Typ
500
500
—
—
© December 2009 Altera Corporation
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
(Part 2 of 2) (Preliminary)
C8
Max
550
—
—
1
Switching Characteristics
402.5
402.5
(Note 1)
Max
320
320
320
320
320
640
640
640
640
640
200
550
55
1
Unit
ms
ps
ps
ps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ps
ps
%
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