EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 304
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 304 of 350
- Download datasheet (8Mb)
1–20
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications
Cyclone III Device Handbook, Volume 2
t
t
t
Notes to
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
(2) t
f
clock
frequency)
Device
operation in
Mbps
t
TCCS
Output jitter
(peak to
peak)
t
t
t
Notes to
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported
(3) t
RISE
FALL
LOCK
HSC LK
DUTY
RISE
FALL
LOCK
Symbol
Symbol
(2)
(3)
at the output pin of all I/O banks.
LOC K
LOC K
(input
Table
Table
is the time required for the PLL to lock from the end of device configuration.
is the time required for the PLL to lock from the end of device configuration.
1–27:
1–28:
20 – 80%,
C
20 – 80%,
C
20 – 80%,
C
20 – 80%,
C
LOAD
LOAD
LOAD
LOAD
Modes
= 5 pF
= 5 pF
Modes
= 5 pF
= 5 pF
—
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
Min
—
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
500
500
Typ
C6
—
C6
Typ
500
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
Max
200
200
200
200
200
400
400
400
400
400
400
400
200
500
55
—
—
—
—
1
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
Min
—
—
—
C7, I7
C7, I7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
Typ
—
155.5
155.5
155.5
155.5
155.5
(Note 1)
Max
311
311
311
311
311
311
311
200
500
55
—
—
1
Max
—
—
1
,
(2)
Min
Chapter 1: Cyclone III Device Data Sheet
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
(Note 1)
Min
—
—
—
© January 2010 Altera Corporation
C8, A7
C8, A7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
Typ
—
(Part 2 of 2)
Switching Characteristics
155.5
155.5
155.5
155.5
155.5
Max
311
311
311
311
311
311
311
200
550
Max
55
—
—
1
—
—
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ms
ms
ps
ps
ps
ps
ps
ps
%
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