EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 168
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 168 of 350
- Download datasheet (8Mb)
9–8
Configuration Process
Cyclone III Device Handbook, Volume 1
f
The output resistance of the repeater buffers must fit the maximum overshoot
equation shown in
Equation 9–1.
Note to
(1)
This section describes the configuration process.
For more information about the configuration cycle state machine of Altera
refer to the
Handbook.
Power Up
If the device is powered up from the power-down state, the V
must be powered up to the appropriate level for the device to exit POR.
To begin configuration, the required voltages listed in
to the appropriate voltage levels.
Table 9–4. Power-Up Voltage for Cyclone III Device Family Configuration
Reset
When nCONFIG or nSTATUS is low, the device is in reset. Upon power-up, the
Cyclone III device family goes through POR. POR delay is dependent on the MSEL
pin settings, which correspond to the configuration scheme that you selected.
Depending on the configuration scheme, either a fast or standard POR time is
available. The fast POR time is 3 ms < TPOR < 9 ms for a fast configuration time. The
standard POR time is 50 ms < TPOR < 200 ms, which has a lower power-ramp rate.
During POR, the device resets, holds nSTATUS and CONF_DONE low, and tri-states all
user I/O pins. When the device exits POR, all user I/O pins continue to tri-state. The
user I/O pins and dual-purpose I/O pins have weak pull-up resistors that are always
enabled (after POR) before and during configuration. After POR, the Cyclone III
device family releases nSTATUS, which is pulled high by an external 10-kΩ pull-up
resistor and enters configuration mode.
When nCONFIG goes high, the device exits reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins.
Notes to
(1) Voltages must be powered up to the appropriate voltage levels to begin configuration.
(2) V
Z
Cyclone III LS
O
CCIO
Equation
is the transmission line impedance and R
Cyclone III
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Device
Table
is for banks in which the configuration and JTAG pins reside.
Configuring Altera FPGAs
9–4:
9–1:
(Note 1)
Equation
9–1:
0.8 Z O R E 1.8Z O
chapter in volume 1 of the Configuration
Voltage that must be Powered-Up
≤
E
V
is the equivalent resistance of the output buffer.
CCBAT
≤
V
CCINT
, V
CCINT
, V
CCA
, V
, V
Table 9–4
CCA
CCIO
, V
© December 2009 Altera Corporation
CCIO
(2)
CCIO
(2)
must be powered up
for all the I/O banks
(1)
Configuration Features
®
FPGAs,
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