EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 207
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–14. FPP Timing Parameters for Cyclone III Device Family
© December 2009
t
t
t
t
t
t
t
t
t
t
t
t
f
t
CF 2CD
CF 2ST0
CF G
STATUS
CF 2ST1
CF 2CK
ST2C K
DSU
DH
CH
CL
CLK
M AX
CD2UM
Symbol
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA setup time before rising edge on DCLK
DATA hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
CONF_DONE high to user mode
Altera Corporation
FPP Configuration Timing
Figure 9–23
external host.
Figure 9–23. FPP Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and
(2) After power-up, the Cyclone III device family holds nSTATUS low during POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. It must be driven high or low, whichever is more convenient.
(5) DATA[7..0] is available as user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
Table 9–14
CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
settings.
CONF_DONE (3)
Figure
nSTATUS (2)
INIT_DONE
DATA[7..0]
nCONFIG
DCLK
User I/O
Parameter
lists the FPP configuration timing parameters for Cyclone III device family.
shows the timing waveform for FPP configuration when using an
9–23:
Tri-stated with internal pull-up resistor
t
t
CFG
CF2CD
(3)
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
Byte 0
STATUS
t
CH
t
CLK
t
DSU
t
Byte 1
CL
t
DH
Byte 2
(Note 1)
Byte 3
(Note 1)
Minimum
(Part 1 of 2)
230
500
300
3.2
3.2
7.5
—
—
45
—
—
2
5
0
(2)
Byte n-1
Byte n
Cyclone III Device Handbook, Volume 1
t
CD2UM
Maximum
(5)
230
230
100
500
500
650
—
—
—
—
—
—
—
—
User Mode
(2)
(2)
(4)
User Mode
(4)
MHz
Unit
μs
μs
μs
μs
μs
9–47
ns
ns
ns
ns
ns
ns
ns
ns