EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 341
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side
Table 2–34. Cyclone III LS Devices Memory Output Clock Jitter Specifications
© December 2009
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
Note to
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
Memory Standard
and row I/Os.
clock network.
Table
Table
2–33:
2–34:
Parameter
Altera Corporation
Table 2–34
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
I/O Standard
lists the Cyclone III LS devices memory ouput clock jitter specifications.
t
t
t
J IT
J IT
J IT
(per)
(cc)
(duty)
1025
1010
1010
1040
1180
1010
1160
1040
1190
1076
1061
1061
Lead
Column I/Os (ps)
915
880
910
961
924
956
Symbol
C7
C8
I7
410
545
340
380
450
570
440
600
360
410
490
630
431
572
357
399
473
599
Lag
Lead
1025
1010
1010
1040
1180
1010
1160
1040
1190
1076
1061
1061
–125
–200
–150
915
880
910
961
924
956
Min
Row I/Os (ps)
(Note 1), (2)
Lag
410
545
340
380
450
570
440
600
360
410
490
630
431
572
357
399
473
599
Cyclone III Device Handbook, Volume 2
Max
(Note 1)
125
200
150
Wraparound Mode (ps)
1015
1125
1010
1010
1110
1140
1280
1110
1260
1140
1290
1061
1176
1024
1161
1056
1161
Lead
980
Unit
ps
ps
ps
510
440
550
670
540
460
510
590
730
531
457
499
573
699
Lag
645
480
700
672
2–23