EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 163
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Configuration Data Decompression
© December 2009
1
1
1
1
Altera Corporation
When using a serial configuration scheme such as PS or fast AS, the configuration
time is the same whether or not you have enabled the design security feature. A ×4
DCLK is required if you use the FPP scheme with the design security feature.
Cyclone III devices support remote system upgrade in AS and AP configuration
schemes. Cyclone III LS devices only support remote system upgrade in the AS
configuration scheme.
This section only describes the decompression feature. For more information about
the design security and remote system upgrade, refer to
page 9–73
Cyclone III device family supports configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration devices or other memory and send the
compressed bitstream to Cyclone III device family. During configuration, Cyclone III
device family decompress the bitstream in real time and program SRAM cells. The
decompression feature is not supported when you have enabled the design security
feature.
Preliminary data indicates that compression reduces configuration bitstream size by
35 to 55%.
Cyclone III device family supports decompression in the AS and PS configuration
schemes. Decompression is not supported in the AP, FPP, or JTAG-based
configuration schemes. In PS mode, use the Cyclone III device family decompression
feature to reduce configuration time.
Altera recommends using the Cyclone III device family decompression feature during
AS configuration if you must save configuration memory space in the serial
configuration device.
When you enable compression, the Quartus II software generates configuration files
with compressed configuration data. This compressed file reduces the storage
requirements in the configuration device or flash memory and decreases the time
needed to send the bitstream to the Cyclone III device family. The time needed by a
Cyclone III device family to decompress a configuration file is less than the time
needed to send the configuration data to the device. There are two methods for
enabling compression for Cyclone III device family bitstreams in the Quartus II
software:
■
■
To enable compression in the compiler settings of the project in the Quartus II
software, perform the following steps:
1. On the Assignments menu, click Device. The Settings dialog box appears.
2. Click Device and Pin Options. The Device and Pin Options dialog box appears.
3. Click the Configuration tab.
Before design compilation (using the Compiler Settings menu).
After design compilation (use the Convert Programming Files dialog box).
and
“Remote System Upgrade” on page
9–77.
“Design Security” on
Cyclone III Device Handbook, Volume 1
9–3