EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 108
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
6–8
Table 6–3. Selectable I/O Drivers for On-Chip Series Termination with and Without Calibration Setting (Part 2 of 2)
On-Chip Series Termination with Calibration
Cyclone III Device Handbook, Volume 1
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
I/O Standard
The Cyclone III device family supports on-chip series termination with calibration in
all banks. The on-chip series termination calibration circuit compares the total
impedance of the I/O buffer to the external 25-Ω ±1% or 50-Ω ±1% resistors
connected to the RUP and RDN pins, and dynamically adjusts the I/O buffer
impedance until they match (as shown in
The R
the I/O buffer.
Figure 6–2. Cyclone III Device Family On-Chip Series Termination with Calibration
OCT with calibration is achieved using the OCT calibration block circuitry. There is
one OCT calibration block in banks 2, 4, 5, and 7. Each calibration block supports each
side of the I/O banks. Because there are two I/O banks sharing the same calibration
block, both banks must have the same V
two related banks have different V
resides can enable OCT calibration.
On-Chip Series Termination with Calibration
S
shown in
Row I/O
50
25
50
25
50
25
50
—
Setting, in ohms (Ω)
Figure 6–2
Driver Series Termination
Cyclone III Device Family
Column I/O
is the intrinsic impedance of the transistors that make up
50
25
50
25
50
25
50
25
V
GND
CCIO
CCIO
R
R
S
S
s, only the bank in which the calibration block
CCIO
Figure
On-Chip Series Termination Without Calibration
Chapter 6: I/O Features in the Cyclone III Device Family
if both banks enable OCT calibration. If
Z
6–2).
O
Row I/O
50
25
50
25
50
25
50
—
Setting, in ohms (Ω)
Receiving
© December 2009 Altera Corporation
Device
Column I/O
50
25
50
25
50
25
50
25
OCT Support