EP3SL150F1152C4N Altera, EP3SL150F1152C4N Datasheet - Page 98

• Manufacturer Part Number: EP3SL150F1152C4N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 744
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Operating Frequency Max: 717MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 1152
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Core Supply Voltage: 1.1V
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2407; EP3SL150F1152C4NES

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Figure 4–17. Stratix III Shift-Register Memory Configuration
ROM Mode
FIFO Mode
Stratix III Device Handbook, Volume 1
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Figure 4–17
All Stratix III TriMatrix memory blocks support ROM mode. A .mif file initializes the
ROM content of these blocks. The address lines of the ROM are registered on M9K
and M144K blocks, but can be unregistered on MLABs. The outputs can be registered
or unregistered. Output registers can be asynchronously cleared. The ROM read
operation is identical to the read operation in the single-port RAM configuration.
All TriMatrix memory blocks support FIFO mode. MLABs are ideal for designs with
many small, shallow FIFO buffers. To implement FIFO buffers in your design, use the
Quartus II software FIFO MegaWizard Plug-In Manager. Both single and dual-clock
(asynchronous) FIFOs are supported.
For more information about implementing FIFO buffers, refer to the
Dual-Clock FIFO Megafunctions User
MLABs do not support mixed-width FIFO mode.
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
shows the TriMatrix memory block in shift-register mode.
Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Guide.
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© May 2009 Altera Corporation
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