EP3SL150F1152C4N Altera, EP3SL150F1152C4N Datasheet - Page 79
EP3SL150F1152C4N
Manufacturer Part Number
EP3SL150F1152C4N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
4.EP3SL150F1152C4N.pdf
(341 pages)
Specifications of EP3SL150F1152C4N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix III
Number Of Logic Blocks/elements
142500
# I/os (max)
744
Frequency (max)
450MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.1V
Logic Cells
142500
Ram Bits
6543360
Operating Supply Voltage (min)
1.05V
Operating Supply Voltage (max)
1.15V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Operating Frequency Max
717MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
1152
Filter Terminals
SMD
Rohs Compliant
Yes
Core Supply Voltage
1.1V
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2407
EP3SL150F1152C4NES
EP3SL150F1152C4NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP3SL150F1152C4N
Manufacturer:
ALTERA
Quantity:
20 000
- EP3SL150F780C4N PDF datasheet
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- EP3SL150F1152C4N PDF datasheet #4
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Chapter 3: MultiTrack Interconnect in Stratix III Devices
Conclusion
Figure 3–10. Column I/O Block Connection to Interconnect
Conclusion
© October 2008 Altera Corporation
R4 Interconnects
Local Interconnect
Interconnects
from Logic Array
LAB Local
Stratix III devices consist of an array of logic blocks such as LABs, TriMatrix memory,
DSP blocks, and IOEs. These blocks communicate with themselves and one another
through the MultiTrack interconnect structures. The Quartus II compiler
automatically routes critical design paths on faster interconnects to improve design
performance and optimize the device resources.
Control Signals
LAB
I/O Block
52 Data &
C4 Interconnects
C12 Interconnects
Vertical I/O Block
52
MLAB
IO_dataina[3:0]
IO_datainb[3:0]
Stratix III Device Handbook, Volume 1
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
LAB
3–13
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