EP3SL150F1152C4N Altera, EP3SL150F1152C4N Datasheet - Page 59

• Manufacturer Part Number: EP3SL150F1152C4N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 744
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Operating Frequency Max: 717MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 1152
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Core Supply Voltage: 1.1V
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2407; EP3SL150F1152C4NES

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Adaptive Logic Modules
Figure 2–13. ALM in Shared Arithmetic Mode
© February 2009 Altera Corporation
datae0
datae1
datab
dataa
datad
datac
You can find adder trees in many different applications. For example, the summation
of the partial products in a logic-based multiplier can be implemented in a tree
structure. Another example is a correlator function that can use a large adder tree to
sum filtered data samples in a given time frame to recover or to de-spread data that
was transmitted utilizing spread spectrum technology.
An example of a three-bit add operation utilizing the shared arithmetic mode is
shown in
obtained using the LUTs, while the result (R[3..0]) is computed using the dedicated
adders.
Figure
2–14. The partial sum (S[3..0]) and the partial carry (C[3..0]) is
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
carry_out
carry_in
labclk
D
D
reg0
reg1
Q
Q
To general or
To general or
To general or
To general or
Stratix III Device Handbook, Volume 1
local routing
local routing
local routing
local routing
2–15