EP3SL150F1152C4N Altera, EP3SL150F1152C4N Datasheet - Page 419

• Manufacturer Part Number: EP3SL150F1152C4N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 744
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Operating Frequency Max: 717MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 1152
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Core Supply Voltage: 1.1V
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2407; EP3SL150F1152C4NES

Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
Chapter Revision History
Chapter Revision History
Table 13–8. Chapter Revision History
© July 2010
July 2010
March 2010
May 2009
February 2009
October 2008
May 2008
November 2007
October 2007
May 2007
November 2006
Date
Altera Corporation
Table 13–8
Version
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
lists the revision history for this chapter.
Updated
Updated for the Quartus II software version 9.1 SP2 release:
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Removed “Referenced Documents” section.
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Updated Table 13–2.
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Initial Release.
Removed “IEEE Std. 1149.1 BST for Configured Devices” and “Conclusion” section.
Updated Table 13–5.
Updated Table 13–1.
Updated “I/O Voltage Support in JTAG Chain” and “IEEE Std. 1149.1 BST Circuitry”
sections.
Updated Table 13–4.
Updated New Document Format.
Updated Table 13–2 and Table 13–5 with EP3SL150ES information.
Updated Table 13–6.
Updated Figure 13–6.
Added new section “Referenced Documents”.
Added live links for references.
Updated Note 3 to Table 13–3. Updated Figure 13–6.
Added Table 13–2, Table 13–4, Table 13–5, and Table 13–7.
Removed opening paragraph and footnote for “IEEE Std. 1149.1 BST Operation
Control” on page 13–9.
Added warning on page 13-22.
Table
13–1.
Changes Made
Stratix III Device Handbook, Volume 1
13–21