EP3SL150F1152C4N Altera, EP3SL150F1152C4N Datasheet - Page 159

• Manufacturer Part Number: EP3SL150F1152C4N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 744
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Operating Frequency Max: 717MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 1152
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Core Supply Voltage: 1.1V
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2407; EP3SL150F1152C4NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
Clock Networks in Stratix III Devices
Table 6–6. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 4)
Table 6–7. Stratix III Device PLLs and PLL Clock Pin Drivers (Part 1 of 2)
© July 2010
RCLK6
RCLK7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
RCLK17
RCLK18
RCLK19
RCLK20
RCLK21
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
Dedicated Clock Input Pin
Clock Resource
(CLKp/n pins)
Altera Corporation
Table 6–6
device Quadrant 4. A given clock input pin can drive two adjacent regional clock
networks to create a dual-regional clock network.
Table 6–7
v
v
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0
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v
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v
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1
lists the connectivity between the dedicated clock input pins and RCLKs in
lists the dedicated clock input pin connectivity to Stratix III device PLLs.
v
v
v
v
L1
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v
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2
v
v
v
v
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—
—
L2
—
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—
v
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—
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—
—
3
v
v
v
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—
—
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—
—
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—
—
—
L3
v
v
v
v
—
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—
—
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—
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4
—
—
—
v
—
—
—
v
—
—
—
v
—
—
—
—
5
v
v
v
v
—
—
—
—
—
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—
—
—
L4
v
v
—
—
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—
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—
—
—
—
6
B1
—
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—
—
v
v
v
v
—
—
—
—
—
CLK (p/n Pins)
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—
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—
v
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v
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7
B2
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—
—
v
v
v
v
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PLL Number
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8
(Note 1)
R1
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v
v
v
v
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9
R2
v
v
v
v
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10
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Stratix III Device Handbook, Volume 1
11
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R3
v
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v
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12
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R4
v
v
v
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v
T1
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14
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T2
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v
15
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6–11