EP1C6F256C6 Altera, EP1C6F256C6 Datasheet - Page 51
![IC CYCLONE FPGA 5980 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP1C6F256C6
Manufacturer Part Number
EP1C6F256C6
Description
IC CYCLONE FPGA 5980 LE 256-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6F256C6
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1018
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C6F256C6
Manufacturer:
ALTERA
Quantity:
10
Company:
Part Number:
EP1C6F256C6N
Manufacturer:
Altera
Quantity:
135
Part Number:
EP1C6F256C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–32. Cyclone IOE in Bidirectional I/O Configuration
Altera Corporation
May 2008
Column or Row
Interconect
ioe_clk[5..0]
comb_datain
data_in
Chip-Wide Reset
OE
clkout
aclr/prn
ce_in
ce_out
clkin
sclr/preset
The Cyclone device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinatorial logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
ENA
PRN
ENA
PRN
ENA
Q
Q
Q
Pin Delay
Drive Strength Control
Output
Open-Drain Output
Slew Control
Input Register Delay
Logic Array Delay
Logic Array Delay
or Input Pin to
Input Pin to
Input Pin to
V
CCIO
V
CCIO
Optional
PCI Clamp
I/O Structure
Preliminary
Bus Hold
Programmable
Pull-Up
Resistor
2–45