EPF8452AQC160-4 Altera, EPF8452AQC160-4 Datasheet - Page 62
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EPF8452AQC160-4
Manufacturer Part Number
EPF8452AQC160-4
Description
IC FLEX 8000A FPGA 4K 160-PQFP
Manufacturer
Altera
Series
FLEX 8000r
Datasheet
1.EPF8282ATC100-3.pdf
(62 pages)
Specifications of EPF8452AQC160-4
Number Of Logic Elements/cells
336
Number Of Labs/clbs
42
Number Of I /o
120
Number Of Gates
4000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-MQFP, 160-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-2259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF8452AQC160-4
Manufacturer:
GENESIS
Quantity:
569
Part Number:
EPF8452AQC160-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 8000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Unused dedicated inputs should be tied to ground on the board.
(11) SDOUT does not exist in the EPF8636GC192 device.
(12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices.
(13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins.
(14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is
Revision
History
62
Perform a complete thermal analysis before committing a design to this device package. See
(Evaluating Power for Altera Devices)
This pin is a dedicated pin and is not available as a user I/O pin.
SDOUT will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the
MAX+PLUS II software will not use SDOUT as a user I/O pin; the user can override the MAX+PLUS II software and
use SDOUT as a user I/O pin.
If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin.
JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins.
If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration.
TRST is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used.
Pin 52 is a V
The user I/O pin count includes dedicated input pins and all I/O pins.
not used, TDI, TCK, TMS, and TRST should be tied to GND.
CC
pin on EPF8452A devices only.
The information contained in the FLEX 8000 Programmable Logic Device
Family Data Sheet version 11.1 supersedes information published in
previous versions. The FLEX 8000 Programmable Logic Device Family Data
Sheet version 11.1 contains the following change: minor textual updates.
for more information.
Application Note 74
Altera Corporation