EPF8452AQC160-4 Altera, EPF8452AQC160-4 Datasheet - Page 12
![IC FLEX 8000A FPGA 4K 160-PQFP](/photos/6/70/67068/544-160-pqfp_sml.jpg)
EPF8452AQC160-4
Manufacturer Part Number
EPF8452AQC160-4
Description
IC FLEX 8000A FPGA 4K 160-PQFP
Manufacturer
Altera
Series
FLEX 8000r
Datasheet
1.EPF8282ATC100-3.pdf
(62 pages)
Specifications of EPF8452AQC160-4
Number Of Logic Elements/cells
336
Number Of Labs/clbs
42
Number Of I /o
120
Number Of Gates
4000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-MQFP, 160-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-2259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF8452AQC160-4
Manufacturer:
GENESIS
Quantity:
569
Part Number:
EPF8452AQC160-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 8000 Programmable Logic Device Family Data Sheet
12
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the
MAX+PLUS II Compiler automatically selects the carry-in or the DATA3
signal as an input. The LUT output can be combined with the cascade-in
signal to form a cascade chain through the cascade-out signal. The LE-Out
signal—the data output of the LE—is either the combinatorial output of
the LUT and cascade chain, or the data output (Q)of the programmable
register.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
provides a 3-bit function; the other generates a carry bit. As shown in
Figure 6, the first LUT uses the carry-in signal and two data inputs from
the LAB local interconnect to generate a combinatorial or registered
output. For example, in an adder, this output is the sum of three bits: a, b,
and the carry-in. The second LUT uses the same three signals to generate
a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports a cascade chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, synchronous
up/down control, and data loading options. These control signals are
generated by the data inputs from the LAB local interconnect, the carry-in
signal, and output feedback from the programmable register. Two 3-input
LUTs are used: one generates the counter data, and the other generates the
fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data
can also be loaded asynchronously with the clear and preset register
control signals, without using the LUT resources.
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control; the clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used: one generates the counter data, and
the other generates the fast carry bit. Synchronous loading is provided by
a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a
synchronous clear.
Altera Corporation