EP2C8F256C7 Altera, EP2C8F256C7 Datasheet - Page 151
![IC CYCLONE II FPGA 8K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP2C8F256C7
Manufacturer Part Number
EP2C8F256C7
Description
IC CYCLONE II FPGA 8K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8F256C7
Number Of Logic Elements/cells
8320
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
182
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1453
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8F256C7
Manufacturer:
ATI/AMD
Quantity:
1
Company:
Part Number:
EP2C8F256C7
Manufacturer:
ALTERA
Quantity:
1 045
Part Number:
EP2C8F256C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2C8F256C7N
Manufacturer:
ALTERA
Quantity:
104
Part Number:
EP2C8F256C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2008
f
(input
clock
fre-
quency)
HSIODR
t
TCCS
(3)
Output
jitter
(peak to
peak)
t
H S C L K
D U T Y
R I S E
Table 5–50. LVDS Transmitter Timing Specification (Part 1 of 2)
Symbol
Conditions
20–80%
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
Min
100
150
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
–6 Speed Grade
Tables 5–50
devices. Cyclone II devices support LVDS receivers at data rates up to
805 Mbps, and LVDS transmitters at data rates up to 640 Mbps.
Typ
200
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
402.5 402.5
402.5 402.5
Max
320
320
320
320
320
640
640
640
640
640
(1)
—
55
200
500
250
and
Max
320
320
320
320
320
640
640
640
640
640
160
(2)
—
5–51
Min
100
150
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
show the LVDS timing budget for Cyclone II
–7 Speed Grade
Typ
200
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC Characteristics and Timing Specifications
402.5 402.5
402.5 402.5
Max
275
275
275
275
275
550
550
550
550
550
(1)
—
55
500
250
200
Cyclone II Device Handbook, Volume 1
312.5
Max
320
320
320
320
320
640
640
640
640
640
(2)
—
Min
100
150
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
–8 Speed Grade
Typ
200
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
402.5
402.5
155.5
155.5
155.5
155.5
155.5
Max
311
311
311
311
311
(1)
(4)
(4)
(4)
(4)
(4)
(8)
(5)
(5)
(5)
(5)
(5)
(9)
55
—
550
250
200
(10)
(11)
402.5
402.5
363.6
Max
320
320
320
320
320
550
550
550
550
550
(2)
(6)
(6)
(6)
(6)
(6)
(8)
(7)
(7)
(7)
(7)
(7)
(9)
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
5–61
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
ps
ps
%