EP1C6Q240C6N Altera, EP1C6Q240C6N Datasheet - Page 55
![IC CYCLONE FPGA 5980 LE 240-PQFP](/photos/6/72/67260/544-240-pqfp_sml.jpg)
EP1C6Q240C6N
Manufacturer Part Number
EP1C6Q240C6N
Description
IC CYCLONE FPGA 5980 LE 240-PQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6Q240C6N
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
5980
# I/os (max)
185
Frequency (max)
405.2MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
5980
Ram Bits
92160
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1811
EP1C6Q240C6N
EP1C6Q240C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C6Q240C6N
Manufacturer:
ALTERA
Quantity:
203
Part Number:
EP1C6Q240C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–34. DDR SDRAM and FCRAM Interfacing
Altera Corporation
May 2008
PLL
OE
Phase Shifted -90˚
Register
OE LE
Register
OE LE
GND
V
CC
Output LE
Output LE
Register
Register
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the I
Programmable
Delay Chain
clk
DQS
Δ t
OE
Register
OE LE
Global Clock
Register
OE LE
DataA
DataB
Output LE
Output LE
Registers
Registers
-90˚ clk
DQ
Adjacent LAB LEs
Register
Register
LE
LE
Registers
Registers
Input LE
Input LE
I/O Structure
Preliminary
Adjacent
LAB LEs
Resynchronizing
Global Clock
OH
/I
2–49
OL