XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 363
![IC FPGA VIRTEX-4 FX 12K 668FCBGA](/photos/6/73/67303/xc4vfx12-10ffg668c_sml.jpg)
XC4VFX12-10FFG668C
Manufacturer Part Number
XC4VFX12-10FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10FFG668C
Total Ram Bits
663552
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
No. Of Logic Blocks
12312
No. Of Macrocells
12312
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1591
XC4VFX12-10FFG668C
XC4VFX12-10FFG668C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC4VFX12-10FFG668C PDF datasheet
- XC4VFX12-10FFG668C PDF datasheet #2
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- Download datasheet (6Mb)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Clock Event 1
•
•
Clock Event 2
•
Clock Event 9
•
TCE
At time T
High at the TCE input of the ODDR 3-state registers, enabling them for incoming
data. Since the TCE signal is common to all ODDR registers, care must be taken to
toggle this signal between the rising edges and falling edges of C as well as meeting
the register setup-time relative to both clock edges.
At time T
valid-High at the T1 input of 3-state register 1 and is reflected on the TQ output at
time T
At time T
valid-High at the T2 input of 3-state register 2 and is reflected on the TQ output at
time T
At time T
synchronous reset in this case) becomes valid-High resetting 3-state Register 1,
reflected at the TQ output at time T
in this case) and resetting 3-state Register 2, reflected at the TQ output at time T
after Clock Event 10 (no change at the TQ output in this case)
SR
TQ
T1
T2
C
T OCKQ
Figure 7-29: OLOGIC ODDR 3-State Register Timing Characteristics
OCKQ
OCKQ
OTCECK
OTCK
OTCK
OSRCK
1
after Clock Event 1.
after Clock Event 2 (no change at the TQ output in this case).
T OTCECK
T OTCK
before Clock Event 1 (rising edge of C), the 3-state signal T1 becomes
before Clock Event 2 (falling edge of C), the 3-state signal T2 becomes
before Clock Event 9 (rising edge of C), the SR signal (configured as
before Clock Event 1, the 3-state clock enable signal becomes valid-
2
www.xilinx.com
3
T OTCK
4
RQ
5
after Clock Event 9 (no change at the TQ output
6
T OSRCK
7
8
9
OLOGIC Resources
10
T RQ
ug070_7_29_080104
11
RQ
363
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