XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 248
![IC FPGA VIRTEX-4 FX 12K 668FCBGA](/photos/6/73/67303/xc4vfx12-10ffg668c_sml.jpg)
XC4VFX12-10FFG668C
Manufacturer Part Number
XC4VFX12-10FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10FFG668C
Total Ram Bits
663552
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
No. Of Logic Blocks
12312
No. Of Macrocells
12312
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1591
XC4VFX12-10FFG668C
XC4VFX12-10FFG668C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 6: SelectIO Resources
248
IOBUF
IBUFDS and IBUFGDS
OBUFDS
The IOBUF primitive is needed when bidirectional signals require both an input buffer and
a 3-state output buffer with an active High 3-state pin.
FPGA IOBUF.
The usage and rules corresponding to the differential primitives are similar to the single-
ended SelectIO primitives. Differential SelectIO primitives have two pins to and from the
device pads to show the P and N channel pins in a differential pair. N channel pins have a
“B” suffix.
Figure 6-21
Figure 6-22
Figure 6-21: Differential Input Buffer Primitive (IBUFDS/IBUFGDS)
shows the differential input buffer primitive.
shows the differential output buffer primitive.
Figure 6-22: Differential Output Buffer Primitive (OBUFDS)
Figure 6-20: Input/Output Buffer (IOBUF) Primitive
3-state input
from FPGA
O (Output)
to FPGA
I (Input)
www.xilinx.com
Input from
Device Pads
Inputs from
T
FPGA
IB
I
I
IOBUF
IBUFDS/IBUFGDS
+
–
+
–
OBUFDS
OB
UG070_6_21_031108
O
O
UG070_6_22_031108
Figure 6-20
Output to
FPGA
Output to
Device Pads
I/O
to/from Device Pad
UG070_6_20_031108
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
shows a generic Virtex-4
R
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