XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 177

• Manufacturer Part Number: XC4VFX12-10FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10FFG668C

• Total Ram Bits: 663552
• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 12312
• No. Of Macrocells: 12312
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1591; XC4VFX12-10FFG668C

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Solution Summary
R
Design Files
All the necessary files required for the above design are contained in a ZIP archive
downloadable from the Xilinx website at:
Open the ZIP archive and extract FIFO16_solution3.zip.
The following criteria can be used to choose a particular solution for the design.
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https://secure.xilinx.com/webreg/clickthrough.do?cid=30163
“Solution 1: Synchronous/Asynchronous Clock Work-Arounds”
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“Solution 2: Work-Around Using a Third Fast Clock”
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“Solution 3: FIFO Flag Generator Using Gray Code”
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Design is currently supported in the CORE Generator tool
Design is required to run at the maximum FIFO16 clock rates
Exact values are required for the ALMOSTEMPTY and ALMOSTFULL Flags
Resource utilization is more than that for Solution 2 and Solution 3 (see Solution 1
for details)
Continuous RDCLK and WRCLK are available after RST
Smallest resource utilization is required
RDCLK and WRCLK needs to be intermittently stopped after RST
Design is not required to run at the maximum FIFO16 clock rates (see Solution 2
for more details)
The generation of a third continuous fast clock is feasible
ALMOSTEMPTY and ALMOSTFULL flags can be delayed by from 1 to 2 RDCLK
or WRCLK periods, respectively
Design is required to run at the maximum FIFO16 clock rates
Resource utilization smaller than Solution 1 is required
RDCLK and WRCLK needs to be intermittently stopped after RST
ALMOSTEMPTY and ALMOSTFULL flags need not be exact and can be within a
range.
www.xilinx.com
FIFO16 Error Condition and Work-Arounds
should be used if:
should be used if:
should be used if:
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