XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 164
![IC FPGA VIRTEX-4 FX 12K 668FCBGA](/photos/6/73/67303/xc4vfx12-10ffg668c_sml.jpg)
XC4VFX12-10FFG668C
Manufacturer Part Number
XC4VFX12-10FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10FFG668C
Total Ram Bits
663552
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
No. Of Logic Blocks
12312
No. Of Macrocells
12312
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1591
XC4VFX12-10FFG668C
XC4VFX12-10FFG668C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10FFG668C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 4: Block RAM
FIFO Applications
164
Cascading FIFOs to Increase Depth
Cascading FIFOs to Increase Width
There are various uses for the Virtex-4 FPGA block RAM FIFO:
•
•
Figure 4-22
FIFO in FWFT mode, and uses external resources to connect to the second FIFO. The
ALMOST_FULL_OFFSET of the second FIFO should be four or more. The data latency of
this application can be up to double that of a single FIFO, and the maximum frequency is
limited by the feedback path. The NOR gate is implemented using CLB logic.
As shown in
design. CLB logic is used to implement the AND/OR gates. The maximum frequency can
be limited by the logic gate feedback path.
DIN[71:36]
DIN[35:0]
DIN[3:0]
WRCLK
RDCLK
WRCLK
WREN
Cascading two asynchronous FIFOs to form a deeper FIFO
Building wider asynchronous FIFO by connecting two FIFOs in parallel.
RDEN
RDCLK
WREN
RDEN
shows a way of cascading FIFOs to increase depth. The application sets the first
512 x 72 FIFO
Figure
DIN[3:0]
WREN
RDEN
WRCLK
RDCLK
4-23, the Virtex-4 FPGA FIFO can be cascaded to add width to the
FIFO #1
Figure 4-23: Cascading FIFO by Width
www.xilinx.com
DOUT[3:0]
Figure 4-22: Cascading FIFO
EMPTY
DIN[35:0]
WREN
RDEN
WRCLK
RDCLK
DIN[35:0]
WREN
RDEN
WRCLK
RDCLK
FIFO #1
FIFO #2
DOUT[35:0]
DOUT[35:0]
DIN[3:0]
WREN
RDEN
WRCLK
RDCLK
EMPTY
EMPTY
AFULL
AFULL
FIFO #2
DOUT[3:0]
UG070 (v2.6) December 1, 2008
AFULL
8K x 4 FIFO
Virtex-4 FPGA User Guide
UG070_4_23_030708
UG070_4_24_030708
DOUT[3:0]
DOUT[35:0]
EMPTY
DOUT[71:36]
AFULL
R
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