EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 92
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part 3 of 3)
Table 1–59. EP3SL70 Column Pin Delay Adders for Regional Clock
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
1.8-V
SSTL CLASS I
DIFFERENTIAL
1.8-V
SSTL CLASS I
DIFFERENTIAL
1.8-V
SSTL CLASS I
DIFFERENTIAL
1.8-V
SSTL CLASS II
DIFFERENTIAL
1.8-V
SSTL CLASS II
DIFFERENTIAL
2.5-V
SSTL CLASS I
DIFFERENTIAL
2.5-V
SSTL CLASS I
DIFFERENTIAL
2.5-V
SSTL CLASS II
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
I/O Standard
Parameter
10mA
12mA
16mA
12mA
16mA
8mA
8mA
8mA
Table 1–59
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–59
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Industrial
-0.014
-0.114
0.158
1.642
Fast Model
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
co
and
lists the EP3SL70 column pin delay adders when using the regional clock.
Commercial
Industrial Commercial
3.066
3.063
3.064
3.113
3.089
3.071
3.117
3.102
3.091
3.071
3.068
3.073
3.066
3.094
3.076
3.062
-0.012
-0.116
0.168
1.675
Table 1–60
Fast Model
-0.007
-0.137
3.298
3.296
3.296
3.349
3.325
3.306
3.352
3.337
3.326
3.306
3.302
3.306
3.299
3.328
3.311
3.295
1.1 V
0.225
2.599
V
C2
CCL
list the EP3SL70 regional clock (RCLK) adder values that
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
-0.003
-0.139
0.241
2.912
1.1 V
V
4.690 5.103 5.629 5.485 5.684 5.238 5.766 5.622 5.751
4.691 5.106 5.632 5.488 5.687 5.241 5.770 5.626 5.755
4.681 5.094 5.619 5.475 5.674 5.228 5.756 5.612 5.741
4.752 5.167 5.695 5.551 5.750 5.302 5.832 5.688 5.817
4.734 5.150 5.678 5.534 5.733 5.285 5.817 5.673 5.802
4.712 5.128 5.656 5.512 5.711 5.263 5.795 5.651 5.780
4.752 5.167 5.694 5.550 5.749 5.302 5.832 5.688 5.817
4.738 5.152 5.679 5.535 5.734 5.287 5.817 5.673 5.802
4.733 5.149 5.676 5.532 5.731 5.284 5.815 5.671 5.800
4.710 5.125 5.653 5.509 5.708 5.261 5.791 5.647 5.776
4.706 5.122 5.649 5.505 5.704 5.257 5.788 5.644 5.773
4.697 5.110 5.635 5.491 5.690 5.244 5.772 5.628 5.757
4.696 5.111 5.638 5.494 5.693 5.247 5.777 5.633 5.762
4.724 5.138 5.664 5.520 5.719 5.273 5.802 5.658 5.787
4.709 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772
4.686 5.099 5.624 5.480 5.679 5.234 5.762 5.618 5.747
1.1 V
C3
V
CCL
C2
CCL
=
=
-0.002
-0.141
0.257
3.223
1.1 V
V
1.1 V
V
C3
C4
CCL
CCL
=
=
1.1 V
V
-0.005
-0.137
0.247
3.071
C4
CCL
1.1 V
V
CCL
=
=
C4L
1.1 V
V
CCL
-0.215
0.313
0.191
0.9 V
V
3.22
=
CCL
C4L
=
0.9 V
V
CCL
© July 2010 Altera Corporation
-0.003
-0.132
=
0.244
2.931
1.1 V
V
CCL
I3
=
1.1 V
V
I3
CCL
=
-0.003
-0.133
0.258
3.238
1.1 V
V
CCL
I4
1.1 V
V
=
I4
CCL
=
I/O Timing
-0.004
-0.136
0.252
3.083
1.1 V
V
CCL
1.1 V
V
CCL
=
=
I4L
I4L
-0.215
0.315
0.191
3.338
0.9 V
V
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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