EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 9

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–13. Single-Ended I/O Standards Specifications
© July 2010 Altera Corporation
3.3-V LVTTL
3.0-V LVTTL
3.3-V LVCMOS
3.0-V LVCMOS
2.5-V LVTTL/
LVCMOS
1.8-V LVTTL /
LVCMOS
1.5-V LVTTL/
LVCMOS
1.2-V LVTTL /
LVCMOS
3.0-V PCI
3.0-V PCI-X
I/O Standard
3.135
3.135
2.375
1.425
Min
2.85
2.85
1.71
1.14
2.85
2.85
V
Internal Weak Pull-Up Resistor
Table 1–12
Table 1–12. Internal Weak Pull-Up Resistor for Stratix III Devices
I/O Standard Specifications
The following tables list input voltage sensitivities (V
(V
supported by Stratix III devices. V
I
Table 1–13
specifications. Refer to
the
CCIO
OL
R
Notes to
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V
(3) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak
Typ
3.3
3.3
2.5
2.5
2.5
1.8
1.5
1.2
Symbol
PU
3
3
3
3
OH
and I
(V)
Table 1–14
pull-down resistor is approximately 25k .
and V
3.465
3.465
2.625
2.625
2.625
1.575
Max Min
3.15
3.15
1.89
1.26
3.15
3.15
Table
OH
, respectively.
Value of the I/O pin pull-
up resistor before and
during configuration, as
well as user mode if the
programmable pull-up
resistor option is
enabled
lists the weak pull-up resistor values for Stratix III devices.
OL
through
1–12:
), and current drive characteristics (I
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
—
—
through
Parameter
V
0.35 * V
0.35 * V
0.35 * V
0.35 * V
IL
0.3 * V
Table 1–18
(V)
Max
0.8
0.8
0.8
0.8
0.7
0.7
0.7
“Glossary” on page 1–326
Table
CCIO
CCIO
CCIO
CCIO
CCIO
1–18.
0.65 * V
0.65 * V
0.65 * V
0.5 * V
0.5 * V
list the Stratix III device family I/O standard
Min
1.7
1.7
1.7
1.7
1.7
1.7
1.7
V
V
V
V
V
V
OL
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
and V
= 3.3 V ± 5%
= 1.8 V ± 5%
V
= 3.0 V ± 5%
= 2.5 V ± 5%
= 1.5 V ± 5%
= 1.2 V ± 5%
IH
Conditions
(V)
V
V
V
CCIO
CCIO
CCIO
OH
Max
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
+ 0.3
+ 0.3
+ 0.3
values are valid at the corresponding
(2)
(2)
(2)
(2)
(2)
(2)
OH
for an explanation of terms used in
0.25 * V
0.25 * V
and I
0.1 * V
0.1 * V
V
IH
Max
0.45
OL
0.4
0.4
0.2
0.2
0.2
0.4
0.7
and V
(V)
(Note
OL
Min
CCIO
CCIO
—
—
—
—
—
—
CCIO
CCIO
Stratix III Device Handbook, Volume 2
) for all I/O standards
IL
1),
0.75 * V
0.75 * V
), output voltages
V
0.9 * V
0.9 * V
V
V
CCIO
V
CCIO
CCIO
(3)
Typ
Min
OH
25
25
25
25
25
25
2.4
2.4
2.1
1.7
2
- 0.45
- 0.2
- 0.2
(V)
CCIO
CCIO
CCIO
CCIO
CCIO
Max
.
—
—
—
—
—
—
(mA)
IOL
0.1
0.1
0.1
1.5
1.5
2
2
1
2
2
2
2
Unit
(mA)
k
k
k
k
k
k
IOH
-0.1
-0.1
-0.1
-0.5
-0.5
-2
-2
-1
-2
-2
-2
-2
1–9