EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 32

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

1–32
Figure 1–5. Output Register Clock to Output Timing Diagram
Stratix III Device Handbook, Volume 2
Datain
Clock
Figure 1–4
Figure 1–4. Input Register Setup and Hold Timing Diagram
For output timing, different I/O standards require different baseline loading
techniques for reporting timing delays. Altera characterizes timing delays with the
required termination for each I/O standard and with 0 pF (except for PCI and PCI-X,
which use 10 pF) loading. The timing is specified up to the output pin of the FPGA
device. The Quartus II software calculates I/O timing for each I/O standard with a
default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera
measures clock-to-output delays (t
maximum temperature (PVT) for default loading conditions listed in
page
Stratix III devices.
The t
+ delay from the clock pad to the I/O output register
+ IOE output register clock-to-output delay
+ delay from the output register to the output pin
Figure 1–5
Simulation using IBIS models is required to determine the delays on the PCB traces in
addition to the output pin delay timing reported by the Quartus II software and the
timing model in the Stratix III Device Handbook. Perform the following steps:
1. Simulate the output driver of choice into the generalized test setup using values
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB trace and load using the
4. Record the time to V
from
appropriate IBIS model or capacitance value to represent the load.
co
1–34. The following equation describes clock-pin-to-output-pin timing for
from the clock pin to the I/O pin =
Table
Clock pad to output
shows the setup and hold timing diagram for input registers.
shows the output register clock to output timing diagram.
Register delay
1–37.
MEAS
MEAS
at the far end of the PCB trace.
at the far end of the PCB trace.
Output Register
Input Clock Delay
Input Data Delay
micro t
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
co
CO
) at worst-case process, minimum voltage, and
Output Register to
output pin delay
micro t
micro t
su
h
© July 2010 Altera Corporation
Output
Table 1–37 on
I/O Timing