EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 16

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Table 1–20. PLL Specifications for Stratix III Devices (Part 3 of 3)
t
t
(7)
f
Notes to
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) This specification is limited by the lower of the two: I/O f
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 120 ps.
(4) F
(5) Peak-to-peak jitter with a probability level of 10
(6) High bandwidth PLL settings are not supported in external feedback mode.
(7) The cascaded PLL specification is only applicable with the following conditions:
(8) External memory interface clock output jitter specifications use a different measurement method and are available in
OUTCCJ_IO
DRIFT
CASC_OUTPJ_DC
Symbol
is applied.
a) Upstream PLL: 0.59 MHz  Upstream PLL BW < 1 MHz
b) Downstream PLL: Downstream PLL BW > 2 MHz
REF
(5),
is fIN/N when N = 1.
Table
(5),
(8)
1–20:
Cycle to Cycle Jitter for clock
output on regular IO
(F
Cycle to Cycle Jitter for clock
output on regular IO
(F
Period Jitter for dedicated clock
output in cascaded PLLs (F
100 MHz)
Period Jitter for dedicated clock
output in cascaded PLLs (F
100 MHz)
Frequency drift after PFDENA is
disabled for duration of 100 s
OUT
OUT
100 MHz)
<100 MHz)
Parameter
–12
OUT
OUT
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps

max
or f
Min
—
—
—
—
—
out
of the PLL.
V
CCL
Typ
= 1.1 V
C2
—
—
—
—
—
Max
600
250
±10
60
25
Min
—
—
—
—
—
V
CCL
C3, I3
Typ
= 1.1 V
—
—
—
—
—
Max
600
250
±10
60
25
Min
—
—
—
—
—
Table 1–33 on page
V
CCL
C4, I4
Typ
= 1.1 V
—
—
—
—
—
Max
600
250
±10
60
25
1–29.
Min
—
—
—
—
—
V
CCL
Typ
= 1.1 V
—
—
—
—
—
Max
600
250
±10
60
25
C4L, I4L
Min
—
—
—
—
—
V
CCL
Typ
= 0.9 V
—
—
—
—
—
Max
32.5
750
325
±10
75
ps (p-p)
ps (p-p)
(p-p)
(p-p)
Unit
mUI
mUI
%