EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 119

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–70. EP3SL110 Row Pin Delay Adders for Regional Clock
Table 1–71. EP3SL150 Column Pins Input Timing Parameters (Part 1 of 3)
© July 2010 Altera Corporation
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
3.0-V
LVCMOS
2.5 V
Standard
I/O
Parameter
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
t
t
t
t
t
t
t
t
t
t
Table 1–70
EP3SL150 I/O Timing Parameters
Table 1–71
devices for single-ended I/O standards.
Table 1–71
I/O standards.
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
Industrial Commercial
-0.072
-0.063
Industrial
0.086
0.075
-0.986
-1.278
-0.986
-1.278
-0.997
-1.289
-0.997
-1.289
-0.992
-1.284
1.119
1.556
1.119
1.556
1.130
1.567
1.130
1.567
1.125
1.562
Fast Model
Fast Model
through
lists the EP3SL110 row pin delay adders when using the regional clock.
lists the EP3SL150 column pins input timing parameters for single-ended
Commercial
-0.097
-0.065
0.109
0.075
-0.964
-1.221
-0.964
-1.221
-0.975
-1.232
-0.975
-1.232
-0.970
-1.227
1.093
1.499
1.093
1.499
1.104
1.510
1.104
1.510
1.099
1.505
Table 1–74
-0.137 -0.135 -0.116 -0.134
-0.097
0.158
0.117
1.1 V
V
-1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106
-1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542
-1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106
-1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542
-1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105
-1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541
-1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105
-1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541
-1.410 -1.572 -1.815 -1.796 -2.124 -1.572 -1.815 -1.796 -2.124
-1.779 -1.998 -2.215 -2.141 -2.560 -1.998 -2.215 -2.141 -2.560
1.584
2.175
1.584
2.175
1.583
2.174
1.583
2.174
1.592
2.183
C2
1.1 V
CCL
V
C2
CCL
=
=
list the maximum I/O timing parameters for EP3SL150
0.123
1.1 V
V
0.16
-0.1
1.767
2.439
1.767
2.439
1.769
2.441
1.769
2.441
1.781
2.453
1.1 V
V
C3
CCL
C3
CCL
=
=
-0.104 -0.101 -0.198 -0.088
0.161
0.129
1.1 V
2.027
2.697
2.027
2.697
2.026
2.696
2.026
2.696
2.045
2.715
V
1.1 V
V
C4
CCL
C4
CCL
=
=
0.159
0.125
1.996
2.598
1.996
2.598
1.995
2.597
1.995
2.597
2.014
2.616
1.1 V
V
1.1 V
V
CCL
CCL
=
=
C4L
C4L
0.281
0.222
-0.24
2.327
3.034
2.327
3.034
2.326
3.033
2.326
3.033
2.345
3.052
0.9 V
0.9 V
V
V
CCL
CCL
Stratix III Device Handbook, Volume 2
=
=
1.767
2.439
1.767
2.439
1.769
2.441
1.769
2.441
1.781
2.453
0.137
0.113
-0.11
1.1 V
1.1 V
V
V
I3
CCL
I3
CCL
=
=
-0.104 -0.124 -0.244
2.027
2.697
2.027
2.697
2.026
2.696
2.026
2.696
2.045
2.715
0.153
0.118
1.1 V
-0.09
V
1.1 V
V
CCL
I4
I4
CCL
=
=
1.996
2.598
1.996
2.598
1.995
2.597
1.995
2.597
2.014
2.616
-0.088 -0.201
1.1 V
0.153
0.114
V
1.1 V
V
CCL
CCL
1–119
=
=
I4L
I4L
2.327
3.034
2.327
3.034
2.326
3.033
2.326
3.033
2.345
3.052
0.9 V
V
0.285
0.226
0.9 V
V
CCL
CCL
=
=
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns