EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 330

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

10–6
Stratix III Device Handbook, Volume 1
f
1
The POR circuit does not monitor the power supplies listed in
Table 10–3. Power Supplies That Are Not Monitored by the POR Circuitry
During power up, all power supplies listed in
to monotonically reach their full-rail values within t
The POR specification is designed to ensure that all the circuits in the Stratix III device
are at certain known states during power up.
The POR signal pulse width is programmable using the PORSEL input pin. When
PORSEL is set to low, the POR signal pulse width is set to 100 ms. A POR pulse width
of 100 ms allows serial flash devices with 65 ms to 100 ms internal POR delay to be
powered up and ready to receive the nSTATUS signal from Stratix III. When the
PORSEL is set to high, the POR signal pulse width is set to 12 ms. A POR pulse width
of 12 ms allows time for power supplies to ramp-up to full rail.
For more information about the POR specification, refer to the
Characteristics
V
V
V
V
V
Note to
(1) The nominal voltage for V
C CIO
C CA _PLL
C CD_P LL
C C_C LK IN
C CB AT
Voltage Supply
Table
10–3:
chapter.
I/O power supply
PLL analog global power supply
PLL digital power supply
PLL differential clock input power supply (top and
bottom I/O banks only)
Battery back-up power supply for design security
volatile key storage
C CB AT
is 3.0-V.
Chapter 10: Hot Socketing and Power-On Reset in Stratix III Devices
Description
Table 10–2
RAMP
.
and
© March 2010 Altera Corporation
Table 10–3
Table
DC and Switching
Power-On Reset Specifications
1.2, 1.5, 1.8, 2.5, 3.0,
3.3
2.5
1.1
2.5
1.0 – 3.3
10–3.
Setting (V)
(1)
are required