EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 270

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

8–22
Figure 8–11. Stratix III DLL and I/O Bank Locations (Package Bottom View)
Stratix III Device Handbook, Volume 1
PLL_L2
PLL_L3
PLL_L4
PLL_L1
1A
1B
1C
2C
2B
2A
DLL0
DLL1
6
6
6
6
The DLL can access the two adjacent sides from its location within the device. For
example, DLL0 on the top left of the device can access the top side (I/O banks 7A, 7B,
7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1B, 1C, 2A, 2B, and
2C). This means that each I/O bank is accessible by two DLLs, giving more flexibility
to create multiple frequencies and multiple-type interfaces. For example, you can
design an interface spanning one side of the device or within two sides adjacent to the
DLL. The DLL outputs the same DQS delay settings for both sides of the device
adjacent to the DLL.
Each bank can use settings from either or both DLLs that the bank is adjacent to. For
example, DQS1L can get its phase-shift settings from DLL0, while DQS2L can get its
phase-shift settings from DLL1.
banks for Stratix III devices.
8A
3A
8B
3B
3C
8C
PLL_T1
PLL_B1
Stratix III FPGA
Table 8–5
PLL_T2
PLL_B2
Chapter 8: External Memory Interfaces in Stratix III Devices
lists the DLL location and supported I/O
7C
4C
4B
7B
Stratix III External Memory Interface Features
© March 2010 Altera Corporation
4A
7A
6
6
DLL3
DLL2
6
6
PLL_R4
PLL_R1
PLL_R3
PLL_R2
6A
6B
6C
5C
5B
5A